1. Field of the Invention
The present invention is related to the field of memory devices. In particular, the present invention is related to Static Random Access Memory (SRAM).
2. Description of the Related Art
SRAM cells are commonly used to store information in electronic circuits. As compared with Dynamic Random Access Memory (DRAM), SRAM have faster access times and do not have to be refreshed. The evolution of smaller SRAM cells, e.g., the four transistor (4T) SRAM cell caused a significant improvement in the storage density on a given piece of silicon as compared with the six transistor (6T) SRAM cell.
FIG. 1 illustrates a conventional 4T SRAM. As illustrated in FIG. 1, a conventional 4T SRAM 100 typically comprises an array or a block of ‘N+1’ rows and ‘M+1’ columns of SRAM cells. Each SRAM cell 105 comprises a matched pair of P-channel Metal Oxide field effect Semiconductor (PMOS) transistors 102A-B (pass transistors) cross coupled with a matched pair of N-channel (NMOS) transistors 104A-B (pull-down transistors). As illustrated in FIG. 1, a storage node 120 is formed by coupling one end of the channel of PMOS transistor 102A, one end of the channel of NMOS transistor 104A, and the gate of NMOS transistor 104B. So also, storage node 125 is formed by coupling one end of the channel of PMOS transistor 102B, one end of the channel of NMOS transistor 104B, and the gate of NMOS transistor 104A. The storage nodes 120 and 125 store a binary bit and its complement respectively. Each PMOS transistor 102A-B has the other end of its channel coupled to a precharge circuit 135, the precharge circuit 135 is coupled to a power supply having a voltage of Vcc volts. As FIG. 1 illustrates, each of the memory cells is coupled to a complementary pair of bitlines, indicated by BL0 and BL0# respectively, which are precharged by the precharge circuit 135 prior to a read or write operation (for a M+1 column SRAM, the M+1 column has bitlines BLM and BLM# respectively).
The gate of each PMOS transistor 102A-B is coupled to a wordline that is driven by a decoder circuit 130. The decoder circuit 130 is coupled to a power supply having a voltage of Vcc volts. The wordlines are indicated by WL0-WLN (for a N+1 row SRAM) in FIG. 1, and are used to selectively enable memory cells to be read from or written to. The other terminal of each NMOS transistor 104A-B is coupled to a global ground connection 110.
Reducing the size of the SRAM cell from six transistors to four transistors, in order to maximize SRAM cell density, causes the 4T SRAM cell to be less stable during read operations and to have a higher off state leakage current as compared with the 6T SRAM cell. This is because in the design of the 6T SRAM cell, the two additional transistors prevent the bits on the storage nodes from changing their state. In addition, during read operations conventional 4T SRAM cells have a slower sensing speed and may leak causing the bits stored on the storage nodes of the SRAM cells to change their state (e.g., from a 0 to a 1 or vice versa). Moreover, in the off state, the 4T SRAM cells have a higher leakage current resulting in a higher power consumption.